1. Field of the Invention
Embodiments of the invention relate generally to memory devices. More particularly, embodiments of the invention relate to a memory device input buffer, memory devices incorporating said input buffer, a memory controller adapted for use with such memory device, and a related memory system.
A claim of priority is made to Korean Patent Application No. 10-2005-0084425, filed on Sep. 10, 2005, the subject matter of which is hereby incorporated by reference.
2. Description of the Related Art
In conventional synchronous memory devices, an input buffer receives an externally transmitted input signal and stores the input signal in accordance with an internal clock signal generated in synchronization with a reference clock.
FIG. 1 is a timing diagram illustrating operation of a conventional memory device. FIG. 1 shows a number of input signals routinely applied to conventional memory devices, including a clock signal (CLK), a chip selection signal (/CS), a row address strobe signal (/RAS), a column address strobe signal (/CAS), a write enable signal (/WE), and address signals (ADDRs). Also in FIG. 1, the period “ts” denotes a setup time period and “th” denotes a hold time period for the various input signals.
In the example illustrated in FIG. 1, setup time “ts” for the respective input signals is a period of time during which each input signal is provided at a defined point of circuitry (e.g., a buffer, latch, flip-flop, etc.) in advance of CLK signal transition (e.g., a transition from low to high at time t1 in the illustrated example). The hold time “th” for the respective input signals is a period of time during which the logical state (a logical “high” or “low”) is maintained following transition of the CLK signal at time t1.
Referring to FIG. 1, the setup time “ts” and the hold time “th” for all of the various input signals are determined in relation to the indicated CLK signal transition at time t1. However, this approach to input signal provision may become problematic problems when the CLK signal is run at high frequency (i.e., transitions rapidly). As the period of the CLK signal decreases with rising frequency, the time available for setup and hold periods becomes increasing limited. Unfortunately, emerging synchronous memory devices are characterized in many instances by an increasing operating speed rate and correspondingly high clock frequencies.
Of additional note, conventional synchronous memory devices are also characterized by a number of different operating modes. These operating modes generally include a power down mode adapted to conserve power consumption and a normal operating (i.e., a non-power down) mode in which operational commands are executed.
Table 1 is a truth table showing selected and commonly used commands (e.g., stand-by, activation, read, write, precharge, and power down) in the context of non-power down and power down operating modes. The state of selected input signals are also illustrated in the context of the commands.
TABLE 1ModeCommandCKE/CS/RAS/CAS/WEADDRNon-PowerStand-byHHXXXXDownActivationHLLLHH/LREADHLHHHH/LWRITEHLHHLH/LPrechargeHLLHLXPower downPower downLXXXXX
In Table 1, H denotes a logically “high” signal state, L denotes a logically “low” signal state, and X denotes a “don't care” state.
FIG. 2 is a block diagram of an input signal portion 200 of a conventional memory device. As shown, input signal portion 200 includes a plurality of input buffers 210 through 270, and a plurality of latch circuits 230-1 through 270-1.
That is, input signal portion 200 of the conventional memory device includes a clock enable (CKE) buffer 210 which receives the CKE signal, a clock (CLK) buffer 220 which receives the CLK signal, a chip selection (CS) buffer 230 which receives the CS signal, a row address strobe (/RAS) buffer 240 which receives the /RAS signal, a column address strobe (/CAS) buffer 250 which receives the /CAS signal, a write enable (/WE) buffer 260 which receives the /WE signal, and an address (ADDR) buffer 270 which receives the ADDR signal.
Input buffers 220 through 270 are enabled and disabled under control of an internal clock enable signal PCKE output by CKE buffer 210.
Input signal portion 200 further includes latch circuits 230-1, 240-1, 250-1, 260-1 and 270-1, as shown in FIG. 2. Latch circuits 230-1 through 270-1 latch the output signals from input buffers 230 through 270, respectively, in response to an internal clock signal PCLK output by CLK buffer 220.
In power down mode (see Table 1), input buffers 220 through 270 are disabled in response to a first logic level of the internal clock enable signal PCKE output by CKE buffer 210 (which remains enabled). In this manner, power consumption otherwise expended by input buffers 220 through 270 is reduced in power down mode. On the other hand, in non-power down mode, input buffers 220 through 270 are enabled in response to a second logic level of the internal clock enable signal PCKE output by CKE buffer 210.
In the context of this exemplary circuitry, and recognizing the difficulty of maintaining adequate setup and hold times for the input signals as the CLK signal increases in frequency, it is generally necessary to continuously enabled of input buffers 220 through 270 in the normal (non-power down) operating mode in order to stably store the various input signals as internal signals in latch circuits 230-1 through 270-1. The power consumed in the normal (non-power down) operating mode by the input buffers is not insignificant, especially when the memory device is utilized in a portable device requiring minimal power consumption. Such portable devices include, as examples, personal digital assistants (PDA), notebook computers, mobile communication devices, and so on.